Decision feedback equalization (DFE) is an important technique in addressing high-frequency attenuation caused by inter-symbol interference (ISI). Generally, at a receiver end of a chip-to-chip interface, the technique involves sampling input data, and compensating for expected ISI by adjusting the sampling based on previously received data values. Partial response methods (i.e., PrDFE) further improve basic DFE techniques by processing parallel decision paths for alternative selection for each sampled input symbol. The parallel paths provide a straightforward way to resolve data decisions using the most recent (least latent) data bits.
As signaling rates increase, feeding back the least latent data in time for use in the processing becomes problematic because of timing delays associated with the feedback path. Elaborating on these delays, the circuitry used to establish this feedback only operates so fast, and as signaling rates increase to the point where a bit timing interval becomes too fast for the circuitry to react, it becomes difficult to effectively utilize feedback representing the least latent prior data. Thus, industry has sought ways for reducing the critical timing paths associated with PrDFE, which would enable these equalizers to work with faster signaling rates.